Micron MT41K256M16TW-107 IT:P SDRAM 4 GB Surface Mount, 96-Pin 16 bit FBGA
- RS Stock No.:
- 696-909
- Mfr. Part No.:
- MT41K256M16TW-107 IT:P
- Manufacturer:
- Micron
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PHP240.10
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PHP268.91
(inc. VAT)
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Units | Per Unit |
|---|---|
| 1 + | PHP240.10 |
*price indicative
- RS Stock No.:
- 696-909
- Mfr. Part No.:
- MT41K256M16TW-107 IT:P
- Manufacturer:
- Micron
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Micron | |
| Memory Size | 4GB | |
| Product Type | SDRAM | |
| Organisation | 256M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 15bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 933MHz | |
| Maximum Random Access Time | 13.91ns | |
| Number of Words | 256 Meg | |
| Mount Type | Surface Mount | |
| Package Type | FBGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 96 | |
| Maximum Operating Temperature | 95°C | |
| Standards/Approvals | RoHS | |
| Width | 8mm | |
| Series | MT41K | |
| Length | 14mm | |
| Height | 1.2mm | |
| Supply Current | 46mA | |
| Maximum Supply Voltage | 1.45V | |
| Minimum Supply Voltage | 1.283V | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Micron | ||
Memory Size 4GB | ||
Product Type SDRAM | ||
Organisation 256M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 15bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 933MHz | ||
Maximum Random Access Time 13.91ns | ||
Number of Words 256 Meg | ||
Mount Type Surface Mount | ||
Package Type FBGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 96 | ||
Maximum Operating Temperature 95°C | ||
Standards/Approvals RoHS | ||
Width 8mm | ||
Series MT41K | ||
Length 14mm | ||
Height 1.2mm | ||
Supply Current 46mA | ||
Maximum Supply Voltage 1.45V | ||
Minimum Supply Voltage 1.283V | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Micron DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an Interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins.
Self refresh temperature
Automatic self refresh
Multipurpose register
RoHS compliant