Nexperia 74AUP2G08DC,125, 2 2-Input AND Schmitt Trigger Input Logic Gate, 8-Pin VSSOP

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Subtotal (1 pack of 25 units)*

PHP505.875

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PHP566.575

(inc. VAT)

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Units
Per Unit
Per Pack*
25 - 225PHP20.235PHP505.88
250 - 600PHP19.729PHP493.23
625 - 1225PHP19.236PHP480.90
1250 - 2475PHP18.755PHP468.88
2500 +PHP18.286PHP457.15

*price indicative

Packaging Options:
RS Stock No.:
153-2935
Mfr. Part No.:
74AUP2G08DC,125
Manufacturer:
Nexperia
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Brand

Nexperia

Product Type

Logic Gate

Logic Function

AND

Mount Type

Surface

Number of Elements

2

Number of Inputs per Gate

2

Schmitt Trigger Input

Yes

Package Type

VSSOP

Pin Count

8

Logic Family

AUP

Input Type

CMOS

Maximum High Level Output Current

-4mA

Maximum Propagation Delay Time @ CL

8.3ns

Minimum Operating Temperature

-40°C

Maximum Operating Temperature

125°C

Standards/Approvals

No

Series

74AUP2G

Width

2.4 mm

Minimum Supply Voltage

0.8V

Height

0.85mm

Maximum Supply Voltage

3.6V

Length

2.1mm

Maximum Low Level Output Current

4mA

Output Type

ECL

Automotive Standard

No

Low-power dual 2-input AND gate, The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

Low static power consumption, ICC = 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of VCC

IOFF circuitry provides partial power-down mode operation

Multiple package options

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