Alliance Memory AS4C32M16D3-12BCNTR SDRAM 512 MB Surface, 96-Pin 16 bit FBGA-96 Ball
- RS Stock No.:
- 425-136
- Mfr. Part No.:
- AS4C32M16D3-12BCNTR
- Manufacturer:
- Alliance Memory
Subtotal (1 reel of 1500 units)*
PHP388,620.00
(exc. VAT)
PHP435,255.00
(inc. VAT)
FREE delivery for orders over ₱3,000.00
Temporarily out of stock
- Shipping from June 10, 2026
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Units | Per Unit | Per Reel* |
|---|---|---|
| 1500 + | PHP259.08 | PHP388,620.00 |
*price indicative
- RS Stock No.:
- 425-136
- Mfr. Part No.:
- AS4C32M16D3-12BCNTR
- Manufacturer:
- Alliance Memory
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 512MB | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 800MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-96 Ball | |
| Pin Count | 96 | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 95°C | |
| Length | 13.10mm | |
| Height | 1mm | |
| Series | AS4C32M16D3 | |
| Standards/Approvals | JEDEC, RoHS | |
| Minimum Supply Voltage | 1.425V | |
| Maximum Supply Voltage | 1.5V | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 512MB | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 800MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-96 Ball | ||
Pin Count 96 | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 95°C | ||
Length 13.10mm | ||
Height 1mm | ||
Series AS4C32M16D3 | ||
Standards/Approvals JEDEC, RoHS | ||
Minimum Supply Voltage 1.425V | ||
Maximum Supply Voltage 1.5V | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Alliance Memory 512Mb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
RoHS compliant
Auto Refresh and Self Refresh
JEDEC Standard Compliant
Related links
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