Vishay DG2517EDN-T1-GE4 Analogue SPDT Switch, 10 CMOS Dual SPDT, Polar, 10-Pin DFN

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PHP625.75

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PHP700.85

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5 - 45PHP125.15PHP625.75
50 - 95PHP116.37PHP581.85
100 - 245PHP112.19PHP560.95
250 - 995PHP109.994PHP549.97
1000 +PHP102.368PHP511.84

*price indicative

Packaging Options:
RS Stock No.:
256-7247
Mfr. Part No.:
DG2517EDN-T1-GE4
Manufacturer:
Vishay
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Brand

Vishay

Logic Family

CMOS

Product Type

Analogue SPDT Switch

Pin Count

10

Number of Elements per Chip

10

Polarity

Polar

Configuration

Dual SPDT

Mount Type

Surface

Package Type

DFN

Minimum Supply Voltage

1.8V

Maximum Supply Voltage

5.5V

Maximum On State Resistance

2.5Ω

Minimum Operating Temperature

-40°C

Maximum Operating Temperature

85°C

Length

900μm

Series

DG2517E

Standards/Approvals

MSL Ratings, JEDEC Standards

Automotive Standard

No

Vishay DG2517E Series Analogue SPDT Switch, 1.8V Minimum Supply Voltage, 2.5Ω Maximum On State Resistance - DG2517EDN-T1-GE4


This analogue SPDT switch is a dual single-pole double-throw CMOS device designed for low-voltage signal routing in surface-mount applications. It operates across a broad supply range and is suited to compact assemblies requiring precise analogue switching with predictable thermal limits and recognised manufacturing-level ratings.

Features and Benefits:


• Operates from 1.8V to 5.5V enabling flexible low-voltage designs
• Maximum on-state resistance 2.5Ω for low-loss signal paths
• CMOS logic family compatibility for simple control interfacing
• Ten-pin DFN package supports high-density surface mounting
• Ambient operating range -40°C to 85°C for varied environments
• MSL and JEDEC conformity simplifies assembly planning

Applications


• Suitable for handheld instrument signal selection
• Ideal for medical monitoring front-end multiplexing
• Used with portable audio routing circuits
• Can be used for test equipment channel switching
• Suitable for compact consumer electronics I/O switching

What mounting method is required for integration?


It is designed for surface-mount placement in a DFN footprint compatible with standard reflow processes.

How many independent switching elements are available on a single device?


The device contains two SPDT switch circuits, allowing multiplexing of two separate signal paths.

What thermal limits should designers plan for during layout?


The device is specified to operate up to 85°C, so thermal dissipation and airflow should maintain junction temperatures within that limit.

Which control signalling levels are supported for logic inputs?


Control inputs conform to CMOS logic thresholds appropriate for the stated supply voltage range.

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