Microchip AT91SAM9G20B-CFU ARM926EJ-S Microprocessor SAM9G20 32 bit ARM 400 MHz 217-Pin BGA
- RS Stock No.:
- 775-373
- Mfr. Part No.:
- AT91SAM9G20B-CFU
- Manufacturer:
- Microchip
N
Subtotal (1 tray of 240 units)*
PHP200,149.44
(exc. VAT)
PHP224,167.44
(inc. VAT)
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Units | Per Unit | Per Tray* |
|---|---|---|
| 240 + | PHP833.956 | PHP200,149.44 |
*price indicative
- RS Stock No.:
- 775-373
- Mfr. Part No.:
- AT91SAM9G20B-CFU
- Manufacturer:
- Microchip
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Series | SAM9G20 | |
| Product Type | Microprocessor | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | ADC, LCD, SPI, USART, USB | |
| Mount Type | Surface Mount | |
| Package Type | BGA | |
| Minimum Supply Voltage | 0.9V | |
| Pin Count | 217 | |
| Maximum Supply Voltage | 1.1V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Automotive Standard | No | |
| Number of Cores | 1 | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Series SAM9G20 | ||
Product Type Microprocessor | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type ADC, LCD, SPI, USART, USB | ||
Mount Type Surface Mount | ||
Package Type BGA | ||
Minimum Supply Voltage 0.9V | ||
Pin Count 217 | ||
Maximum Supply Voltage 1.1V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Automotive Standard No | ||
Number of Cores 1 | ||
- COO (Country of Origin):
- CN
The Microchip embedded processor is designed for multitasking applications, balancing performance with low power consumption. It supports both 32-bit ARM and 16-bit Thumb instruction sets, Ideal for applications requiring efficient code execution.
Supports a Harvard cached architecture for enhanced data throughput
Includes a Memory Management Unit for improved memory efficiency
Features separate instruction and data AMBA AHB bus interfaces to optimise performance
Offers flexibility in cache sizes ranging from 4KB to 128KB for tailored application needs
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