Microchip AT91SAM9CN11-CUR ARM926EJ-S Microprocessor AT91SAM9CN11 32 bit ARM 400 MHz 217-Pin BGA
- RS Stock No.:
- 775-436
- Mfr. Part No.:
- AT91SAM9CN11-CUR
- Manufacturer:
- Microchip
N
Subtotal (1 reel of 500 units)*
PHP303,923.00
(exc. VAT)
PHP340,394.00
(inc. VAT)
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Units | Per Unit | Per Reel* |
|---|---|---|
| 500 + | PHP607.846 | PHP303,923.00 |
*price indicative
- RS Stock No.:
- 775-436
- Mfr. Part No.:
- AT91SAM9CN11-CUR
- Manufacturer:
- Microchip
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Series | AT91SAM9CN11 | |
| Product Type | Microprocessor | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | NAND | |
| Mount Type | Surface Mount | |
| Minimum Supply Voltage | 0.9V | |
| Package Type | BGA | |
| Pin Count | 217 | |
| Maximum Supply Voltage | 1.1V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Number of Cores | 1 | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Series AT91SAM9CN11 | ||
Product Type Microprocessor | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type NAND | ||
Mount Type Surface Mount | ||
Minimum Supply Voltage 0.9V | ||
Package Type BGA | ||
Pin Count 217 | ||
Maximum Supply Voltage 1.1V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Number of Cores 1 | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The Microchip versatile microprocessor is designed for multi-tasking applications, integrating efficient memory management and low power consumption. It supports both ARM and Thumb instruction sets, optimising performance with high code density.
Supports 32-bit ARM and 16-bit Thumb instruction sets for performance flexibility
Includes a Memory Management Unit (MMU) for effective memory control
Features a Harvard cached architecture ensuring high processing efficiency
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