Renesas Electronics 74FCT573CTSOG 8-Bit Octal D Type Latch, Transparent, CMOS, 20-Pin SOIC
- RS Stock No.:
- 263-7966
- Mfr. Part No.:
- 74FCT573CTSOG
- Manufacturer:
- Renesas Electronics
This image is representative of the product range
Bulk discount available
Subtotal (1 pack of 5 units)*
PHP247.00
(exc. VAT)
PHP276.65
(inc. VAT)
Stock information currently inaccessible - Please check back later
Units | Per Unit | Per Pack* |
|---|---|---|
| 5 - 5 | PHP49.40 | PHP247.00 |
| 10 - 20 | PHP44.41 | PHP222.05 |
| 25 - 105 | PHP42.296 | PHP211.48 |
| 110 + | PHP41.45 | PHP207.25 |
*price indicative
- RS Stock No.:
- 263-7966
- Mfr. Part No.:
- 74FCT573CTSOG
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Family | 74FCT | |
| Product Type | Octal D Type Latch | |
| Logic Function | D Type | |
| Latch Mode | Transparent | |
| Number of Bits | 8 | |
| Number of Channels | 20 | |
| Output Type | CMOS | |
| Package Type | SOIC | |
| Pin Count | 20 | |
| Maximum Propagation Delay Time @ CL | 4.2ns | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Family 74FCT | ||
Product Type Octal D Type Latch | ||
Logic Function D Type | ||
Latch Mode Transparent | ||
Number of Bits 8 | ||
Number of Channels 20 | ||
Output Type CMOS | ||
Package Type SOIC | ||
Pin Count 20 | ||
Maximum Propagation Delay Time @ CL 4.2ns | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals No | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Renesas Electronics octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when latch enable is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the output enable is low. When OE is high, the bus output is in the high-impedance state.
Low input and output leakage ≤1μA
CMOS power levels
High drive outputs
Power off disable outputs permit live insertion
Related links
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