onsemi MC74AC273DWR2G Octal D Type Flip Flop IC, CMOS, 20-Pin SOIC
- RS Stock No.:
- 806-2205P
- Mfr. Part No.:
- MC74AC273DWR2G
- Manufacturer:
- onsemi
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RS will no longer stock this product.
- RS Stock No.:
- 806-2205P
- Mfr. Part No.:
- MC74AC273DWR2G
- Manufacturer:
- onsemi
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | onsemi | |
| Logic Family | AC | |
| Logic Function | D Type | |
| Input Type | TTL | |
| Output Type | CMOS | |
| Output Signal Type | Single Ended | |
| Triggering Type | Positive Edge | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SOIC | |
| Pin Count | 20 | |
| Set/Reset | Master Reset | |
| Number of Elements per Chip | 8 | |
| Maximum Propagation Delay Time @ Maximum CL | 12 ns@ 50 pF | |
| Dimensions | 12.95 x 7.6 x 2.4mm | |
| Maximum Operating Supply Voltage | 6 V | |
| Propagation Delay Test Condition | 50pF | |
| Minimum Operating Supply Voltage | 2 V | |
| Length | 12.95mm | |
| Height | 2.4mm | |
| Maximum Operating Temperature | +85 °C | |
| Width | 7.6mm | |
| Minimum Operating Temperature | -40 °C | |
| Select all | ||
|---|---|---|
Brand onsemi | ||
Logic Family AC | ||
Logic Function D Type | ||
Input Type TTL | ||
Output Type CMOS | ||
Output Signal Type Single Ended | ||
Triggering Type Positive Edge | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type SOIC | ||
Pin Count 20 | ||
Set/Reset Master Reset | ||
Number of Elements per Chip 8 | ||
Maximum Propagation Delay Time @ Maximum CL 12 ns@ 50 pF | ||
Dimensions 12.95 x 7.6 x 2.4mm | ||
Maximum Operating Supply Voltage 6 V | ||
Propagation Delay Test Condition 50pF | ||
Minimum Operating Supply Voltage 2 V | ||
Length 12.95mm | ||
Height 2.4mm | ||
Maximum Operating Temperature +85 °C | ||
Width 7.6mm | ||
Minimum Operating Temperature -40 °C | ||
The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip- flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
ACT273 Has TTL Compatible Inputs
