Toshiba 74HC74D 2 Flip Flop IC 74HC, CMOS, 14-Pin SOIC
- RS Stock No.:
- 171-3146
- Mfr. Part No.:
- 74HC74D
- Manufacturer:
- Toshiba
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PHP435.74
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PHP488.02
(inc. VAT)
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Units | Per Unit | Per Pack* |
|---|---|---|
| 20 - 80 | PHP21.787 | PHP435.74 |
| 100 - 480 | PHP21.133 | PHP422.66 |
| 500 - 980 | PHP20.499 | PHP409.98 |
| 1000 + | PHP19.885 | PHP397.70 |
*price indicative
- RS Stock No.:
- 171-3146
- Mfr. Part No.:
- 74HC74D
- Manufacturer:
- Toshiba
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Product Type | Flip Flop IC | |
| Logic Family | 74HC | |
| Output Type | CMOS | |
| Clock Frequency | 29MHz | |
| Polarity | Inverting | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Minimum Supply Voltage | 2V | |
| Pin Count | 14 | |
| Maximum Supply Voltage | 6V | |
| Flip-Flop Type | D Flip-Flop | |
| Minimum Operating Temperature | -40°C | |
| Trigger Type | Positive Edge | |
| Maximum Propagation Delay Time @ CL | 32ns | |
| Number of Elements per Chip | 2 | |
| Maximum Operating Temperature | 85°C | |
| Length | 8.95mm | |
| Height | 1.38mm | |
| Standards/Approvals | No | |
| Series | 74HC74D | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Product Type Flip Flop IC | ||
Logic Family 74HC | ||
Output Type CMOS | ||
Clock Frequency 29MHz | ||
Polarity Inverting | ||
Mount Type Surface | ||
Package Type SOIC | ||
Minimum Supply Voltage 2V | ||
Pin Count 14 | ||
Maximum Supply Voltage 6V | ||
Flip-Flop Type D Flip-Flop | ||
Minimum Operating Temperature -40°C | ||
Trigger Type Positive Edge | ||
Maximum Propagation Delay Time @ CL 32ns | ||
Number of Elements per Chip 2 | ||
Maximum Operating Temperature 85°C | ||
Length 8.95mm | ||
Height 1.38mm | ||
Standards/Approvals No | ||
Series 74HC74D | ||
Automotive Standard No | ||
The 74HC74D is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of theCLOCK pulse. CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: fMAX = 77 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 2.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V
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