Nexperia 74HC574D,652 8 Octal D Type Flip Flop HC, 3 State, 20-Pin SOIC
- RS Stock No.:
- 124-2263
- Mfr. Part No.:
- 74HC574D,652
- Manufacturer:
- Nexperia
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- RS Stock No.:
- 124-2263
- Mfr. Part No.:
- 74HC574D,652
- Manufacturer:
- Nexperia
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Product Type | Octal D Type Flip Flop | |
| Logic Family | HC | |
| Input Type | Single Ended | |
| Output Type | 3 State | |
| Clock Frequency | 24MHz | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 6V | |
| Pin Count | 20 | |
| Flip-Flop Type | Type D | |
| Trigger Type | Positive Edge | |
| Maximum Propagation Delay Time @ CL | 45ns | |
| Minimum Operating Temperature | -40°C | |
| Number of Elements per Chip | 8 | |
| Maximum Operating Temperature | 125°C | |
| Length | 13mm | |
| Height | 2.45mm | |
| Standards/Approvals | JEDEC No. 7A | |
| Series | 74HC | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Product Type Octal D Type Flip Flop | ||
Logic Family HC | ||
Input Type Single Ended | ||
Output Type 3 State | ||
Clock Frequency 24MHz | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SOIC | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 6V | ||
Pin Count 20 | ||
Flip-Flop Type Type D | ||
Trigger Type Positive Edge | ||
Maximum Propagation Delay Time @ CL 45ns | ||
Minimum Operating Temperature -40°C | ||
Number of Elements per Chip 8 | ||
Maximum Operating Temperature 125°C | ||
Length 13mm | ||
Height 2.45mm | ||
Standards/Approvals JEDEC No. 7A | ||
Series 74HC | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TH
The 74HC574, 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Key applications
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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