Renesas Electronics 9DB102BGLFT PLL Clock Buffer 20-Pin TSSOP-20
- RS Stock No.:
- 264-3526
- Mfr. Part No.:
- 9DB102BGLFT
- Manufacturer:
- Renesas Electronics
This image is representative of the product range
Bulk discount available
Subtotal (1 pack of 2 units)*
PHP427.13
(exc. VAT)
PHP478.386
(inc. VAT)
FREE delivery for orders over ₱3,000.00
Last RS stock
- Final 2,994 unit(s), ready to ship from another location
Units | Per Unit | Per Pack* |
|---|---|---|
| 2 - 48 | PHP213.565 | PHP427.13 |
| 50 - 98 | PHP207.155 | PHP414.31 |
| 100 - 248 | PHP200.935 | PHP401.87 |
| 250 - 998 | PHP194.905 | PHP389.81 |
| 1000 + | PHP189.055 | PHP378.11 |
*price indicative
- RS Stock No.:
- 264-3526
- Mfr. Part No.:
- 9DB102BGLFT
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | PLL Clock Buffer | |
| Maximum Input Frequency | 101MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP-20 | |
| Pin Count | 20 | |
| Minimum Supply Voltage | -0.5V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Width | 6.6 mm | |
| Length | 6.4mm | |
| Height | 1.2mm | |
| Series | ICS9DB102 | |
| Standards/Approvals | RoHS | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type PLL Clock Buffer | ||
Maximum Input Frequency 101MHz | ||
Mount Type Surface | ||
Package Type TSSOP-20 | ||
Pin Count 20 | ||
Minimum Supply Voltage -0.5V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Width 6.6 mm | ||
Length 6.4mm | ||
Height 1.2mm | ||
Series ICS9DB102 | ||
Standards/Approvals RoHS | ||
Automotive Standard No | ||
The Renesas Electronics PLL clock is a zero delay buffer which supports PCI Express clocking requirements. It is driven by a differential SRC output pair from an ICS CK410 or CK505 compliant main clock. It attenuates jitter on the input clock and has a selectable PLL band width to maximize performance in systems with or without spread spectrum clocking.
PLL or bypass mode or PLL can dejitter incoming clock available
SMBus interface or unused outputs can be disabled
Industrial temperature range available
Spread Spectrum Compatible or tracks spreading input clock for low EMI
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