Renesas Electronics 9DB233AGILF Clock Buffer 20-Pin TSSOP
- RS Stock No.:
- 263-7982
- Mfr. Part No.:
- 9DB233AGILF
- Manufacturer:
- Renesas Electronics
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Subtotal (1 tube of 74 units)*
PHP15,861.678
(exc. VAT)
PHP17,765.106
(inc. VAT)
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In Stock
- 74 unit(s) ready to ship from another location
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Units | Per Unit | Per Tube* |
|---|---|---|
| 74 - 222 | PHP214.347 | PHP15,861.68 |
| 296 + | PHP203.412 | PHP15,052.49 |
*price indicative
- RS Stock No.:
- 263-7982
- Mfr. Part No.:
- 9DB233AGILF
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 110MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Number of Outputs | 2 | |
| Minimum Supply Voltage | 3.3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Width | 4.4 mm | |
| Height | 1.2mm | |
| Standards/Approvals | RoHS | |
| Series | 9DB233 | |
| Length | 6.6mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 110MHz | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Number of Outputs 2 | ||
Minimum Supply Voltage 3.3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Width 4.4 mm | ||
Height 1.2mm | ||
Standards/Approvals RoHS | ||
Series 9DB233 | ||
Length 6.6mm | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
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