STMicroelectronics STM32G484RET6, 32 bit ARM Cortex M4, STM32G484RE Microcontroller, 170 MHz, 512kB FLASH, 64-Pin LQFP

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PHP552.97

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PHP619.33

(inc. VAT)

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1 - 9PHP552.97
10 - 24PHP536.38
25 - 49PHP520.29
50 - 74PHP504.68
75 +PHP489.54

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Packaging Options:
RS Stock No.:
193-9866
Mfr. Part No.:
STM32G484RET6
Manufacturer:
STMicroelectronics
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Brand

STMicroelectronics

Product Type

Microcontroller

Series

STM32G484RE

Package Type

LQFP

Mount Type

Surface

Pin Count

64

Device Core

ARM Cortex M4

Data Bus Width

32bit

Program Memory Size

512kB

Maximum Clock Frequency

170MHz

RAM Size

128kB

Maximum Supply Voltage

3.6V

Minimum Operating Temperature

-40°C

Maximum Operating Temperature

85°C

Height

1.45mm

Standards/Approvals

No

Length

10mm

Width

40 mm

DACs

7 x 12 Bit

Analogue Comparators

7

Number of Programmable I/Os

107

Minimum Supply Voltage

1.71V

Program Memory Type

FLASH

ADCs

42 x 12 Bit

Automotive Standard

No

Instruction Set Architecture

RISC

Number of Timers

2

COO (Country of Origin):
CN
The STM32G484xx devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 Mhz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security. These devices embed high-speed memories (512 Kbytes of Flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI Flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection.

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