Renesas Electronics 9DB106BGILFT PLL Clock Buffer 28-Pin TSSOP-28
- RS Stock No.:
- 264-3528
- Mfr. Part No.:
- 9DB106BGILFT
- Manufacturer:
- Renesas Electronics
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Subtotal (1 pack of 2 units)*
PHP523.87
(exc. VAT)
PHP586.734
(inc. VAT)
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In Stock
- 1,920 unit(s) ready to ship from another location
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Units | Per Unit | Per Pack* |
|---|---|---|
| 2 - 48 | PHP261.935 | PHP523.87 |
| 50 - 98 | PHP254.08 | PHP508.16 |
| 100 - 248 | PHP246.46 | PHP492.92 |
| 250 - 998 | PHP239.065 | PHP478.13 |
| 1000 + | PHP231.895 | PHP463.79 |
*price indicative
- RS Stock No.:
- 264-3528
- Mfr. Part No.:
- 9DB106BGILFT
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | PLL Clock Buffer | |
| Maximum Input Frequency | 105MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP-28 | |
| Pin Count | 28 | |
| Number of Outputs | 6 | |
| Minimum Supply Voltage | 3.3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -65°C | |
| Maximum Operating Temperature | 150°C | |
| Series | 9DB106 | |
| Standards/Approvals | RoHS | |
| Height | 1.2mm | |
| Length | 6.4mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type PLL Clock Buffer | ||
Maximum Input Frequency 105MHz | ||
Mount Type Surface | ||
Package Type TSSOP-28 | ||
Pin Count 28 | ||
Number of Outputs 6 | ||
Minimum Supply Voltage 3.3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -65°C | ||
Maximum Operating Temperature 150°C | ||
Series 9DB106 | ||
Standards/Approvals RoHS | ||
Height 1.2mm | ||
Length 6.4mm | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Renesas Electronics differential buffer is a zero delay buffer which supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT CK410 or CK505 compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options while 2 clock request pins make the device suitable for express card applications.
SMBus interface or unused outputs can be disabled here
Spread spectrum compatible or tracks spreading input clock for low EMI available
PLL or bypass mode or PLL can dejitter incoming clock present
6 to 0.7 V current mode differential output pairs
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