Renesas Electronics 2309-1HPGG Clock Buffer 16-Pin TSSOP
- RS Stock No.:
- 263-7880
- Mfr. Part No.:
- 2309-1HPGG
- Manufacturer:
- Renesas Electronics
This image is representative of the product range
Bulk discount available
Subtotal (1 pack of 5 units)*
PHP430.20
(exc. VAT)
PHP481.80
(inc. VAT)
FREE delivery for orders over ₱3,000.00
In Stock
- 565 unit(s) ready to ship from another location
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Units | Per Unit | Per Pack* |
|---|---|---|
| 5 - 5 | PHP86.04 | PHP430.20 |
| 10 - 20 | PHP77.292 | PHP386.46 |
| 25 - 45 | PHP72.308 | PHP361.54 |
| 50 - 90 | PHP70.868 | PHP354.34 |
| 95 + | PHP69.428 | PHP347.14 |
*price indicative
- RS Stock No.:
- 263-7880
- Mfr. Part No.:
- 2309-1HPGG
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Number of Outputs | 15 | |
| Minimum Supply Voltage | -0.5V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Standards/Approvals | RoHS | |
| Series | IDT2309 | |
| Width | 4.4 mm | |
| Length | 5mm | |
| Height | 1mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Number of Outputs 15 | ||
Minimum Supply Voltage -0.5V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Standards/Approvals RoHS | ||
Series IDT2309 | ||
Width 4.4 mm | ||
Length 5mm | ||
Height 1mm | ||
Automotive Standard No | ||
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
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