Renesas Electronics 2305A-1DCGI Clock Buffer 8-Pin SOIC
- RS Stock No.:
- 263-7869
- Mfr. Part No.:
- 2305A-1DCGI
- Manufacturer:
- Renesas Electronics
This image is representative of the product range
Bulk discount available
Subtotal (1 pack of 5 units)*
PHP436.51
(exc. VAT)
PHP488.89
(inc. VAT)
FREE delivery for orders over ₱3,000.00
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- 775 left, ready to ship from another location
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Units | Per Unit | Per Pack* |
|---|---|---|
| 5 - 5 | PHP87.302 | PHP436.51 |
| 10 - 20 | PHP78.746 | PHP393.73 |
| 25 - 45 | PHP74.732 | PHP373.66 |
| 50 - 90 | PHP73.26 | PHP366.30 |
| 95 + | PHP71.788 | PHP358.94 |
*price indicative
- RS Stock No.:
- 263-7869
- Mfr. Part No.:
- 2305A-1DCGI
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 8 | |
| Minimum Supply Voltage | -0.5V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Series | IDT2305A | |
| Length | 4.9mm | |
| Width | 3.9 mm | |
| Height | 1.5mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 8 | ||
Minimum Supply Voltage -0.5V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Series IDT2305A | ||
Length 4.9mm | ||
Width 3.9 mm | ||
Height 1.5mm | ||
Automotive Standard No | ||
- COO (Country of Origin):
- PH
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
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