Renesas Electronics 9DB106BGLFT Buffer 28-Pin TSSOP
- RS Stock No.:
- 235-8708
- Mfr. Part No.:
- 9DB106BGLFT
- Manufacturer:
- Renesas Electronics
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Subtotal (1 reel of 2000 units)*
PHP465,208.00
(exc. VAT)
PHP521,032.00
(inc. VAT)
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- Shipping from May 11, 2026
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Units | Per Unit | Per Reel* |
|---|---|---|
| 2000 + | PHP232.604 | PHP465,208.00 |
*price indicative
- RS Stock No.:
- 235-8708
- Mfr. Part No.:
- 9DB106BGLFT
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Buffer | |
| Maximum Input Frequency | 105MHz | |
| Mount Type | Surface | |
| Maximum Propagation Delay Time | 150ps | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| Number of Outputs | 6 | |
| Minimum Supply Voltage | 3.135V | |
| Maximum Supply Voltage | 3.465V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Length | 9.7mm | |
| Width | 4.4 mm | |
| Series | 9DB106 | |
| Standards/Approvals | PCIe Gen1 and Gen2 | |
| Height | 1mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Buffer | ||
Maximum Input Frequency 105MHz | ||
Mount Type Surface | ||
Maximum Propagation Delay Time 150ps | ||
Package Type TSSOP | ||
Pin Count 28 | ||
Number of Outputs 6 | ||
Minimum Supply Voltage 3.135V | ||
Maximum Supply Voltage 3.465V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Length 9.7mm | ||
Width 4.4 mm | ||
Series 9DB106 | ||
Standards/Approvals PCIe Gen1 and Gen2 | ||
Height 1mm | ||
Automotive Standard No | ||
The Renesas Electronics zero delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The is driven by a differential SRC output pair from an IDT compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread spectrum clocking. An SMBus Interface allows control of the PLL bandwidth and bypass options, while 2 clock request pins make the suitable for Express card applications.
Selectable pll bandwidth minimizes jitter peaking in downstream plls
Spread spectrum compatible tracks spreading input clock for low emi
Smbus Interface unused outputs can be disabled
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