Lattice FPGA ICE40HX4K-TQ144, iCE40 HX 3520 Cells, 80kbit, 440 Blocks, 144-Pin TQFP
- RS Stock No.:
- 168-4222
- Mfr. Part No.:
- ICE40HX4K-TQ144
- Manufacturer:
- Lattice Semiconductor
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Subtotal (1 tray of 60 units)*
PHP38,798.40
(exc. VAT)
PHP43,454.40
(inc. VAT)
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In Stock
- Plus 420 unit(s) shipping from December 08, 2025
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Units | Per Unit | Per Tray* |
|---|---|---|
| 60 + | PHP646.64 | PHP38,798.40 |
*price indicative
- RS Stock No.:
- 168-4222
- Mfr. Part No.:
- ICE40HX4K-TQ144
- Manufacturer:
- Lattice Semiconductor
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Lattice Semiconductor | |
| Family Name | iCE40 HX | |
| Number of Logic Cells | 3520 | |
| Number of Logic Units | 440 | |
| Number of Registers | 3520 | |
| Mounting Type | Surface Mount | |
| Package Type | TQFP | |
| Pin Count | 144 | |
| Number of RAM Bits | 80kbit | |
| Dimensions | 20 x 20 x 1.45mm | |
| Height | 1.45mm | |
| Length | 20mm | |
| Maximum Operating Temperature | +85 °C | |
| Width | 20mm | |
| Maximum Operating Supply Voltage | 1.26 V | |
| Minimum Operating Supply Voltage | 1.14 V | |
| Minimum Operating Temperature | -40 °C | |
| Select all | ||
|---|---|---|
Brand Lattice Semiconductor | ||
Family Name iCE40 HX | ||
Number of Logic Cells 3520 | ||
Number of Logic Units 440 | ||
Number of Registers 3520 | ||
Mounting Type Surface Mount | ||
Package Type TQFP | ||
Pin Count 144 | ||
Number of RAM Bits 80kbit | ||
Dimensions 20 x 20 x 1.45mm | ||
Height 1.45mm | ||
Length 20mm | ||
Maximum Operating Temperature +85 °C | ||
Width 20mm | ||
Maximum Operating Supply Voltage 1.26 V | ||
Minimum Operating Supply Voltage 1.14 V | ||
Minimum Operating Temperature -40 °C | ||
- COO (Country of Origin):
- KR
Field Programmable Gate Arrays, Lattice Semiconductor
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB.
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