Microchip DSPIC33EP256MC204, 16 bit Digital Signal Processor 70 MHz 256kB FLASH 44-Pin TQFP

This image is representative of the product range

Subtotal (1 tray of 160 units)*

PHP44,489.92

(exc. VAT)

PHP49,828.64

(inc. VAT)

Add to Basket
Select or type quantity
Temporarily out of stock
  • Shipping from June 08, 2026
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units
Per Unit
Per Tray*
160 +PHP278.062PHP44,489.92

*price indicative

RS Stock No.:
177-3513
Mfr. Part No.:
DSPIC33EP256MC204-I/PT
Manufacturer:
Microchip
Find similar products by selecting one or more attributes.
Select all

Brand

Microchip

Maximum Clock Frequency

70MHz

Product Type

Digital Signal Processor

Series

DSPIC33EP256MC204

Device Million Instructions per Second

70MIPS

Data Bus Width

16bit

RAM Size

32kB

Instruction Set Architecture

Harvard

Program Memory Size

256kB

Program Memory Type

FLASH

Minimum Supply Voltage

3V

Numeric and Arithmetic Format

ALU

Maximum Supply Voltage

3.6V

Mount Type

Surface

Package Type

TQFP

Minimum Operating Temperature

-40°C

Number of ADCs

1

Number of PWM Channels

6

Maximum Operating Temperature

85°C

Pin Count

44

Height

1.05mm

Length

10mm

Standards/Approvals

No

PWM Resolution

16bit

ADC Channels

9

Number of PWM Units

3

Automotive Standard

AEC-Q100

ADC Resolution

12bit

Timer Resolution

32bit

Microchip’s dsPIC33E family of digital signal controllers (DSCs) features a 70 MIPS dsPIC® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation, have a great range and extended life. They can be used to control brushless DC, permanent magnet synchronous, AC induction and stepper motors. These devices are also ideal for high-performance general purpose applications.

Operating Conditions

3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS

3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS

dsPIC33E Core

Modified Harvard Architecture

C Compiler Optimized Instruction Set

16-bit Wide Data Path

24-bit Wide Instructions

16x16 Integer Multiply Operations

32/16 and 16/16 Integer Divide Operations

11 Additional Instructions

Two 40-bit Accumulators with Rounding and Saturation Options