Renesas Electronics 8305AGILF Clock Buffer, 16-Pin 4 TSSOP
- RS Stock No.:
- 216-6204
- Mfr. Part No.:
- 8305AGILF
- Manufacturer:
- Renesas Electronics
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Subtotal (1 pack of 2 units)*
PHP532.56
(exc. VAT)
PHP596.46
(inc. VAT)
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Last RS stock
- Final 68 unit(s), ready to ship from another location
Units | Per Unit | Per Pack* |
|---|---|---|
| 2 - 8 | PHP266.28 | PHP532.56 |
| 10 - 18 | PHP258.295 | PHP516.59 |
| 20 - 48 | PHP247.96 | PHP495.92 |
| 50 - 98 | PHP235.56 | PHP471.12 |
| 100 + | PHP221.43 | PHP442.86 |
*price indicative
- RS Stock No.:
- 216-6204
- Mfr. Part No.:
- 8305AGILF
- Manufacturer:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 1.8V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 4.9mm | |
| Height | 1.2mm | |
| Standards/Approvals | No | |
| Series | 8305A | |
| Width | 6.4 mm | |
| Automotive Standard | No | |
| Number of Outputs | 4 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 1.8V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 4.9mm | ||
Height 1.2mm | ||
Standards/Approvals No | ||
Series 8305A | ||
Width 6.4 mm | ||
Automotive Standard No | ||
Number of Outputs 4 | ||
The Renesas Electronics ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
4 LVCMOS/LVTTL outputs
Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
Maximum output frequency: 350MHz
Output skew: 40ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant